1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for increasing the carrier mobility of the semiconductor device.
2. Description of Related Art
The metal-oxide semiconductor (MOS) transistor having low electrical consumption is appropriate for the high density integration process. Therefore, a MOS transistor is the most widely applied in basic electronic devices. As the integration of semiconductor devices continues to increase, the dimension of the MOS transistor reduces correspondingly. However, any further size reduction is limited. Therefore, other approaches, for example, by increasing the strain of the transistor's channel to improve the carrier mobility, are currently being evaluated.
For an N-type metal oxide semiconductor transistor, forming a silicon nitride layer having a tensile stress on the N-type MOS transistor is a common method used in increasing the strain of the channel. Further, the increase of the electron mobility is directly proportional to the stress of the silicon nitride film. Accordingly, the stress of the silicon nitride film can be used to control the increase of the electron mobility of the N-type MOS transistor. The higher the stress of the silicon nitride film, the better the electron mobility is resulted.
On the other hand, for a P-type MOS transistor, the higher the tensile stress of the silicon nitride film, the hole mobility decays correspondingly. In order to form both of the P-type MOS transistor and the N-type MOS transistor, the conventional method is to remove a portion of the silicon nitride layer over the P-type MOS transistor and then to remove the rest of the silicon nitride layer over the N-type MOS transistor after the strain of the channel of the N-type MOS transistor is increased. However, in the two-step silicon nitride removal process, the silicon nitride residue or the over etching issue easily happen at the interface between the P-type MOS transistor and the N-type MOS transistor.
FIG. 1 is a cross-sectional view showing a conventional semiconductor device. FIG. 2 is a cross-sectional view showing another conventional semiconductor device. As shown in FIG. 1, during the silicon nitride layer over the N-type MOS transistor 102a is removed and the pattern mask layer over the P-type MOS transistor 102b overlaps a portion of the silicon nitride layer, some of the silicon nitride layer 104 still remains on the substrate 100. On the other hand, as shown in FIG. 2, during the silicon nitride layer over the N-type MOS transistor 202a is removed and the pattern mask layer over the P-type MOS transistor 202b draws back toward to the P-type MOS transistor 202b so as to expose a portion of the isolation structure or the substrate 200, an over etching issue happens. That is, the isolation structure or the substrate 200 is damaged to form the crack 204 therein during the silicon nitride layer is removed. Accordingly, the performance of the semiconductor device is degraded and the yield is decreased.